A low-power encoder architecture for pyramid vector quantization of 2D subband coefficients

This paper describes a VLSI architecture designed to pyramid vector quantize (PVQ) 2-D subband image for low-power portable applications. Using the 0.8 μ CMOS process, the chip is estimated to dissipate less than 300 μW at a 1.5 V supply, encoding at 1.27 Mpixels/sec, for display of 240 pixels wide, 176 lines, and 30 frames per second, while introducing no noticeable degradation in the decompressed video quality. Low power consumption is achieved through efficient algorithm-to-hardware mapping requiring no multipliers, dividers, or external memory accesses, innovative computational methods, and reduction in supply voltage