A timing analysis tool for VLSI CMOS synchronous circuits

Timing modeling and analysis of VLSI CMOS circuits is a very important part of the practice in design of complex digital circuits. The tool named TIME, a timing analyzer developed to utilize a timing model we introduced recently, is described in this paper. Its implementation is briefly described, and emphasis is given in this paper to the description of the semi-empirical modeling of delays in complex circuits. The model we introduce has a latency time in addition to a linear-RC estimate, aiming at an increased accuracy on the estimation of gate delays by taking a transistor-level description of VLSI circuits. The results obtained by the implementation of the delay model in the TIME tool are herein described. The tool can predict delays in synchronous circuits with errors of less than 6% when compared to SPICE electrically simulated delays, and comparisons to the predictions of the timing model proposed by Horowitz (1984) and of the timing verifier CRYSTAL are also shown