Design and implementation of a scalable floating-point FFT IP core for Xilinx FPGAs

Implementing floating-point (FP) Fast Fourier Transforms (FFT) on Field Programmable Gate Arrays (FPGAs) still represents a challenging task. The limited resources on target devices coupled with the inherent complexity of the FFT are among factors limiting widespread utilization. This paper presents the design of a scalable, FP FFT core for synthesis on Xilinx FPGAs. Its architecture uses a radix-2 Pease formulation scalable in the number of points, operand precision, number of butterflies, and transform direction. A bottom-up methodology documents the design of its internal components. Results of resource consumption and performance up to 116 megapoints per second were obtained, evaluating all implementable scenarios in single and double precision IEEE-754 standard.