Title :
Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits
Author :
Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
In this paper, we consider the problem of finding all-pairs input-to-output delays for combinational circuits. This method is of practical utility in several design situations and CAD algorithms. An algorithm for solving this problem was proposed by Fishburn (1990); however, this can be computationally expensive. We take advantage of some properties of large realistic circuits to present an algorithm that is two orders of magnitude faster than the aforementioned method for large circuits. Experimental results on ISCAS benchmark circuits prove the efficacy of this approach
Keywords :
PERT; circuit analysis computing; combinational circuits; critical path analysis; delays; integrated logic circuits; logic CAD; sequential circuits; timing; CAD algorithms; PERT algorithm; all-pairs input-to-output delays; combinational blocks; critical paths; large circuits; synchronous sequential circuits; Algorithm design and analysis; Clocks; Combinational circuits; Delay estimation; Design automation; Flip-flops; Propagation delay; Sequential circuits; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.542015
