An efficient hardware design tool for scalable matrix multiplication

Matrix operations are required in many complex algorithms in digital, image and video processing applications. The conventional method is usually used to implement matrix multiplications for small matrices. However, with the development of VLSI technology and FPGAs, there is an increasing demand for developing a high speed, low power and low area matrix multiplication system for large matrices. The design and verification process of an area-efficient and high throughput matrix multiplication operator can be time consuming and complex. In this study, an efficient hardware design tool is developed to generate a matrix multiplication operator based on user input parameters using three different approaches (Conventional, Strassen, and Hybrid). Strassen algorithm can be used to reduce the area of the matrix multiplication system; nevertheless this method increases the memory requirements and decreases the accuracy of the results. The proposed Hybrid-Strassen matrix multiplication algorithm increases the precision of the operation while reducing the area of the overall system compared to a conventional approach. The generated design has been implemented on Xilinx Virtex-5 FPGAs but can be synthesized for VLSI implementations.