Reducing Parasitic Electrical Parameters with a Planar Interconnection Packaging Structure

Author

Liang, Zhenxian ; Ning, Puqi ; Wang, Fred ; Marlino, Laura

Author_Institution

Oak Ridge Nat. Lab., Oak Ridge, TN, USA

fYear

2012

Firstpage

1

Lastpage

6

Abstract

A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. The power switches in a popular phase leg electrical topology are orientated in a face up/face down configuration. Large bonding areas between dies and substrates combined with a compact busbar interface allow this packaging technology to offer dramatic improvements in electrical conversion efficiency and electromagnetic interference containment.

Keywords

electromagnetic interference; electronics packaging; power semiconductor switches; substrates; electrical conduction; electrical conversion efficiency; electromagnetic interference containment; insulation functions; medium power modules; parasitic electrical parameters; planar interconnection packaging structure; power semiconductor switches; power switches; symmetric substrates; Inductance; Insulated gate bipolar transistors; Integrated circuit interconnections; Multichip modules; Switches; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Power Electronics Systems (CIPS), 2012 7th International Conference on

Conference_Location

Nuremberg

Print_ISBN

978-3-8007-3414-6

Type

conf

Filename

6170650