Title :
A method for efficient implementation of reliable processors
Author :
Marques, Elaine C. ; Naviner, Lirida A B ; Naviner, Jean Francois
Author_Institution :
Inst. TELECOM, TELECOM ParisTech, Paris, France
Abstract :
Reliability is becoming an important feature of digital circuits implemented on deep submicron technologies. Fault tolerance techniques can be used in order to improve the circuit´s reliability but leading to some kind of design penalties (area, time, power consumption). In this work, we propose a method that takes into account reliability and other classic design parameters when choosing the most suitable architecture. In addition, the designer is free to establish different cost-performance tradeoffs according to the target application.
Keywords :
circuit reliability; digital circuits; fault tolerance; microprocessor chips; circuit reliability; deep submicron technologies; design penalties; digital circuits; fault tolerance; reliable processors; Circuits; Costs; Energy consumption; Failure analysis; Fault tolerance; Fault tolerant systems; Manufacturing processes; Nanoscale devices; Redundancy; Telecommunications;
Conference_Titel :
Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-7771-5
DOI :
10.1109/MWSCAS.2010.5548767
