Area optimized multiplier using flow retiming and input data folding

This paper presents a 16-bit area enhanced modular multiplier. The proposed multiplier uses 4-bit multipliers as building blocks. Significant area reduction is realized via hardware reuse. Reduction of 4-bit multiplier instances was achieved using multiplication flow retiming (iteration) and input operands reordering (folding) techniques. Implementation results show that the proposed architecture has area advantage over existing ones such as Wallace and 4-bit Modular multipliers.