A 125-ps access, 4GHZ, 16Kb BiCMOS SRAM

Author

Liu, Xuelian ; Aquino, Hadrian Olayvar ; Gutin, Alexey ; Mcdonald, John

Author_Institution

Electr., Comput. & Syst. Eng., Renssenlaer Polytech. Inst., Troy, NY, USA

fYear

2010

Firstpage

1222

Lastpage

1225

Abstract

A 128Kbit BiCMOS SRAM with a typical access time of 125ps was developed with 0.13um IBM Silicon Germanium BiCMOS technology. The fast access time with moderate power dissipation has been achieved using following techniques: CML decoder, CML driver circuit, bipolar sense amplify. CMOS 6T memory cell is used to achieve the high packing density. The simulation demonstrates that this SRAM macro can achieve working frequency of 4GHZ. This Macro is especially useful for realizing ultrahigh speed, high density SRAMs which is used as cache in the super computing processor.

Keywords

BiCMOS integrated circuits; SRAM chips; BiCMOS SRAM; CML decoder; CML driver circuit; CMOS 6T memory cell; IBM Silicon Germanium BiCMOS technology; bipolar sense amplify; frequency 4 GHz; size 0.13 mum; time 125 ps; word length 128000 bit; word length 16000 bit; BiCMOS integrated circuits; CMOS technology; Circuit simulation; Computational modeling; Decoding; Driver circuits; Germanium silicon alloys; Power dissipation; Random access memory; Silicon germanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Conference_Location

Seattle, WA

ISSN

1548-3746

Print_ISBN

978-1-4244-7771-5

Type

conf

DOI

10.1109/MWSCAS.2010.5548773

Filename

5548773