Large system asynchronous design

Author

Johansen, Donald E.

Author_Institution

jLogic Associates, Reading, MA, USA

fYear

1993

Firstpage

207

Lastpage

213

Abstract

A language is presented for the design of asynchronous logic circuits. The language offers effective syntax for specifying long-range interactions among signals remote from one another in the data pipeline. Problems specified in the language have a unique-state-coding implicit in their formulation. Solutions are fully interlocked and satisfy properties of liveness, safeness, and persistency. Features of the language are presented with two examples. One involves the design of an asynchronous 3:1 parallel multiplexer involving concepts of bundled data paths and control. The other illustrates the synthesis of self-timed data paths of a type described by T.E. Williams and M.A. Horowitz (1991)

Keywords

VLSI; application specific integrated circuits; asynchronous circuits; hardware description languages; high level languages; logic CAD; multiplexing equipment; 3:1 parallel multiplexer; ASIC; CAD; PRODIAC; VLSI; asynchronous logic circuits; bundled data paths; high-level language; interlocked circuits; self-timed data paths; self-timed design; synthesis; unique-state-coding; Asynchronous circuits; Clocks; Logic circuits; Logic design; Multiplexing; Petri nets; Pipelines; Registers; Signal design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410707

Filename

410707