Title :
Gate-first process and EOT-scaling of III-V nanowire-based vertical transistors on Si
Author :
Tomioka, Katsuhiro ; Fukui, T.
Author_Institution :
GS of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
Abstract :
Non-planar III-V MOSFETs are promising candidate transistor for future n-MOSFET with low power and high speed. Recently, bottom-up In0.7Ga0.3As nanowire-channels on Si have been reported. However, the report was limited to large-sized nanowire-channels and EOT is much thicker than the practical devices. In this presentation, we advances the device fabrication by using completely gate-first process and investigate the EOT scaling from 0.70 nm to 2.75 nm. Furthermore, we investigate diameter-scaling of InGaAs/InAlAs/InP core-multishell nanowire-HEMT structure with thin EOT.
Keywords :
III-V semiconductors; MOSFET; aluminium compounds; gallium arsenide; indium compounds; nanowires; silicon; EOT-scaling; III-V nanowire-based vertical transistors; InGaAs-InAlAs-InP; Si; core-multishell nanowire-HEMT structure; device fabrication; gate-first process; n-MOSFET; nanowire-channels; nonplanar III-V MOSFET; size 0.7 nm to 2.75 nm; Fabrication; HEMTs; Indium gallium arsenide; Logic gates; Silicon;
Conference_Titel :
Device Research Conference (DRC), 2013 71st Annual
Conference_Location :
Notre Dame, IN
Print_ISBN :
978-1-4799-0811-0
DOI :
10.1109/DRC.2013.6633772