Parallel `ATOM´ switch architecture for high-speed ATM networks

The authors propose a parallel ATOM (asynchronous transfer mode output modular) switch architecture, capable of handling multi-gigabit per second lines. It is composed of distributors, a number of switch planes, and resequencers. A simple resequencing method is also proposed to keep sequence integrity for cells sent out from different switch planes. It is shown that the memory access speed requirement can be reduced dramatically, as the number of switch planes increases. With this architecture, for example, a 9.6 Gb/s per line 32 by 32 ATM switch can be achieved using 70 Mb/s BiCMOS technologies. Performance evaluations by computer simulation show that additional delay and buffer memories for resequencing are much smaller than for conventional methods, and that they pose no practical problem