Highly linear very compact untrimmed on-chip temperature sensor with second and third order temperature compensation

This paper proposes a CMOS structure as a highly linear on-chip temperature sensor. As long as all transistors are in saturation, the output of the structure is a V_DD independent voltage source that linearly expresses CMOS threshold voltage, and hence is approximately linear in temperature. A new sizing strategy is introduced following a combined analytical and numerical optimization approach, which effectively removes both second and third order nonlinearities. Following this sizing approach, the sensor output voltage can be made very linear in temperature, with temperature INL (maximum temperature errors due to Vout temperature nonlinearity) within 0.05°C over the temperature range of -20~100°C. Results from corner simulations and Monte Carlo simulations demonstrate that the sensor linearity has excellent robustness over process variation and local device mismatches. With a standard two point calibration, the sensor´s maximum output error can be confined within 0.15°C without any trimming. The sensor is very compact with a total active area around 200 μm² when implemented in 0.18μm process.