A VLSI design for a real-time video decoder

Author

Chan, Y.K. ; Kwong, S. ; Chan, K.L. ; Wong, T.F.

Author_Institution

Dept. of Comput. Sci., City Univ. of Hong Kong, Kowloon, Hong Kong

fYear

1995

Firstpage

461

Lastpage

469

Abstract

This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a signal-to-noise ratio of 32 dB. It is found that the real-time decoder has a better performance when compared with previous implementations. The static decompression part of the decoder is based on the SDIC algorithm. The major advantage of the SDIC algorithm is the hardware simplicity and its VLSI realization. In this paper, the hardware design of the real-time decoder and results are presented

Keywords

VLSI; data compression; decoding; digital signal processing chips; real-time systems; video coding; SDIC algorithm; SNR; VLSI design; motion CIF format video sequence; real-time video decoder; signal/noise ratio; spatial domain image compression; static decompression; Buffer storage; Decoding; Discrete cosine transforms; Frequency domain analysis; Hardware; Image coding; Transform coding; Very large scale integration; Video compression; Video sharing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]

Conference_Location

Sakai

Print_ISBN

0-7803-2612-1

Type

conf

DOI

10.1109/VLSISP.1995.527517

Filename

527517