An efficient memory fault-test technique for ASIC-based memories

A new test technique that is efficient in terms of additional circuitry and test vectors and is easily implemented as a built-in-self test (BIST) circuit is described. The technique tests the individual memory elements, the input and output data buses, the address decoding circuits, the read and write select lines, the test circuits, and any address or data buffers associated with the memory. The technique provides 100% coverage for stuck-high and stuck-low faults in the memory and test circuits with approximately one vector per bit of memory. At least half of all two-coupled coupling faults that are localized within a single word location and a substantial number of coupling faults between word locations will also be detected. Simulation results are presented, and extensions of the technique, such as fault identification, are also discussed