DocumentCode
1574179
Title
Quality evaluation for silver sintering layers in power electronic modules
Author
Rudzki, Jacek ; Jensen, Lars ; Poech, Max ; Schmidt, Lothar ; Osterwald, Frank
Author_Institution
Danfoss Silicon Power GmbH, Schleswig, Germany
fYear
2012
Firstpage
1
Lastpage
6
Abstract
This publication presents a quality evaluation method based on thermal impedance test (Zth) to detect delaminations in the sintered power modules. For this purpose an emulated delamination has been used as a test standard. Common test methods such a SAM and X-Ray microscopy are also presented and their suitability for testing of sinter layers is discussed. First results for Lock-In thermography for detection of defects in sinter layers are presented. The Zth test method is based on the measurement of the junction temperature Tj of the semiconductor device after a short current pulse. The duration of this current pulse has to be constant for all devices to provide a defined thermal power. A delaminated layer beneath the silicon die corrupts the heat dissipation path and leads to increased junction temperature. The deviation in Tj provides information about the condition of the joining layer between the silicon die and the substrate. Measurement results of the Zth tests are verified by using FEM thermal simulation, SAM and Lock-In thermography. A thermal model to predict the influence of delaminations in the sintered layer on the junction temperature is presented as well.
Keywords
X-ray microscopy; finite element analysis; infrared imaging; power semiconductor devices; semiconductor device manufacture; semiconductor device testing; sintering; temperature measurement; FEM thermal simulation; SAM; X-ray microscopy; Zth test method; defect detection; delamination detection; emulated delamination; heat dissipation path; joining layer; junction temperature measurement; lock-in thermography; power electronic module; quality evaluation; semiconductor device; short current pulse; silver sintering layer; sinter layer testing; sintered power module; thermal impedance test; thermal model; thermal power; Delamination; Heating; Insulated gate bipolar transistors; Metallization; Substrates; Temperature measurement; X-ray imaging;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Power Electronics Systems (CIPS), 2012 7th International Conference on
Conference_Location
Nuremberg
Print_ISBN
978-3-8007-3414-6
Type
conf
Filename
6170692
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