A pA-leakage CMOS charge pump for low-supply PLLs

A potential drain/source swap problem in a traditional low-leakage charge pump under low supply is investigated and the design methodology and results of a low-voltage CMOS charge pump structure for phase-locked loop (PLL) applications are presented. Simulated in a 65-nm CMOS process, the structure is capable of reducing the static leakage current to the pA range while providing close to rail-to-rail output swing, which is needed in low-supply PLLs. Charge injection cancellation is naturally included and no extra dummy devices are needed. The switching speeds also improve. Such low leakage current ensures less than -60 dBc reference spur levels in integer-N PLLs.