DocumentCode
1575063
Title
Embedded memory module design for video signal processing
Author
Chang, Tian-Sheuan ; Jen, Chein-Wei
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
1995
Firstpage
501
Lastpage
510
Abstract
Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency
Keywords
CMOS memory circuits; application specific integrated circuits; video signal processing; 2 Kbit; ASIC; concurrent line access; embedded memory module design; multiport capability; single port cell hardware; video signal processing; Algorithm design and analysis; Bandwidth; Delay lines; HDTV; Parallel processing; Read-write memory; Signal design; Signal processing algorithms; Time sharing computer systems; Video signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]
Conference_Location
Sakai
Print_ISBN
0-7803-2612-1
Type
conf
DOI
10.1109/VLSISP.1995.527521
Filename
527521
Link To Document