Development and validation of dual-core Viterbi

This paper describes a dual-core linear Viterbi IP design which adopts the linear Viterbi algorithm as the algorithm part, and uses pipelined structure through which two Viterbi submodules can translate two unidentified entries at the same time. In the verification phase, FPGA is applied to verify the design and the verification of FPGA needs DEII development board, selects the 50MHz crystal oscillator, customizes three groups of RAM to store parameters by MeGaWizard tool as well. Through the observation and calculation, it can be concluded that the time of one butterfly operation with dual-core Viterbi averages only 22.7ns, approximately one clock cycle, whose computing time is 50% faster than single-core.