• DocumentCode
    1575265
  • Title

    RLRAM: A VLSI implementation of a resetable, loadable RAM module

  • Author

    Papathanassiadis, T. ; Hertzberger, L.O.

  • Author_Institution
    Amsterdam Univ., Netherlands
  • fYear
    1993
  • Firstpage
    239
  • Lastpage
    242
  • Abstract
    The design, implementation, and testing of a 128 × 6 Reset Load RAM (RLRAM) chip is presented. It is a RAM module with additional functionality: one cycle complete RAM reset, and two cycle loading of pre-determined value set, out of eight. The successfully tested 1.5 μm prototype modules run at 35.7 MHz and measure 4 mm2. In spite of the massively parallel operations, supply current measurements show that RLRAM can mix with other digital logic without power surge problems
  • Keywords
    CMOS memory circuits; VLSI; application specific integrated circuits; memory architecture; modules; random-access storage; 35.7 MHz; CMOS; RLRAM chip; VLSI implementation; customized memory cell; floorplan; image block partitioning; loadable RAM module; massively parallel operations; resetable; Clocks; Decoding; Hardware; Image coding; Random access memory; Read only memory; Read-write memory; Testing; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
  • Conference_Location
    Rochester, NY
  • Print_ISBN
    0-7803-1375-5
  • Type

    conf

  • DOI
    10.1109/ASIC.1993.410714
  • Filename
    410714
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1575265