A multiple-bandwidth 12-bit pipelined analog to digital converter with self-clock generator

A multiple-bandwidth 12-bit pipelined analog to digital converter (ADC) with edge-combiner digital delay locked loop for self clock generation and embedded sample & hold (S/H) circuit is presented. The ADC circuit in the proposed design avoids external clock signal for sampling, by generating the clock from analog input signal for a wide range of frequency operation. The proposed design is capable of operating over the input frequency range of 10KHz to 15MHz with 150MSPS maximum sampling frequency. The proposed ADC has been verified for post layout simulations in 90nm CMOS technology which has DNL<; ±0.25LSB, INL<; ±0.5LSB, SNR of 71.5dB, SNDR of 69.1dB and maximum power consumption of 25mw at 12-bit with 150MSPS sampling frequency.