An alternate phase locked loop (APLL) frequency synthesizer employing sample-hold scheme

This paper proposes a novel PLL frequency synthesizer (for mobile data terminals) in which the VCO control voltage is held at a fixed value by employing a sample hold circuit. The proposed synthesizer achieves fast frequency settling times with low power consumption even though it employs two VCOs. Each has a sample-hold circuit and are alternately controlled by only one PLL. Power consumption and frequency error are theoretically and experimentally analyzed. The proposed synthesizer has a 28% lower power consumption than the conventional synthesizer with dual PLLs. The theoretically analyzed frequency errors are shown to be accurate. Both analyses confirm that increasing the acquisition time of the sample-hold circuit reduces the output frequency error during the hold operation