DocumentCode
157560
Title
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis
Author
Saifhashemi, Arash ; Hand, Duncan ; Beerel, Peter A. ; Koven, William ; Hong Wang
Author_Institution
Intel, Hillsboro, OR, USA
fYear
2014
fDate
12-14 May 2014
Firstpage
110
Lastpage
111
Abstract
We describe a method in which resynthesis is applied to the bundled-data implementation of a production-level Intel architecture CPU (Quark) to improve performance and area. A two-step quadratic program is presented for optimally adjusting the new flop-to-flop path constraints for resynthesis. Our experimental results show an average improvement of 25% in performance at the same area cost.
Keywords
circuit optimisation; integrated circuit design; microprocessor chips; quadratic programming; CPU; area optimization; bundled-data Intel processor resynthesis; flop-to-flop path constraints; performance optimization; production-level Intel architecture; two-step quadratic program; Asynchronous circuits; Central Processing Unit; Delays; Latches; Optimization; bundled data; desynchronization; quark; resynthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems (ASYNC), 2014 20th IEEE International Symposium on
Conference_Location
Potsdam
ISSN
1522-8681
Type
conf
DOI
10.1109/ASYNC.2014.25
Filename
6835821
Link To Document