An improved digital-IF transmitter architecture for highly-integrated W-CDMA mobile terminals

An improved digital-IF transmitter architecture for W-CDMA mobile terminals is proposed. Based on the heterodyne design but without requiring any off-chip IF filter, the transmitter enjoys the advantages of a homodyne architecture (such as circuit simplicity low power consumption and high level of integration) while avoiding the performance problems associated with direct up-conversion. By implementing the quadrature modulation in the digital domain, and requiring only a single path of analog baseband circuits, inherently perfect I/Q matching and good EVM (error vector magnitude) performance can be achieved. The intermediate frequency (IF) is chosen to be a quarter of the clock rate for very simple and low power digital modulator design. The difficulties of on-chip IF filtering were greatly alleviated by (a) performing a careful frequency planning, and (b) employing a special-purpose DAC to produce high-order sin(x)/x rolloff. System level simulation demonstrates that spurious-emission requirements are met with virtually no dedicated reconstruction filter circuits. This architecture takes full advantage of CMOS technology scaling by employing digital processing to ease analog complexities.