A 0.5V 2-1 cascaded continuous-time Delta-Sigma modulator synthesized with a new method

This manuscript presents a new method of synthesizing cascaded continuous-time Delta-Sigma Modulators. The coefficients for each stage are obtained by a discrete-time to continuous-time transformation. A detailed derivation of the digital cancellation logics for modulators based on discrete-time domain analysis is presented which leads to a simple implementation of circuits and is capable of correcting the effect of RC value variation. The proposed synthesis method is applied to a 0.5-V 2-1 cascaded continuous-time Delta-Sigma modulator with switched-capacitor-resistor feedback. Transistor-level simulations show that a 98dB SNDR is achieved over a 25kHz signal bandwidth with a 6.4MHz sampling frequency and 350μW power consumption under a 0.5-V supply.