Performance analysis of multiplier using various techniques

Multiplication is that the basic operation. Multipliers have giant space, additional latency and consume additional quantity of power. important factors within the style of multipliers area unit chip space and speed of multiplication and need less hardware. Scaling of technology node will increase power-density over expected. This paper is concentrated on Multi exactitude (MP) reconfigurable number combined with varied exactitude strategies, multiprocessing (PP), razor-based dynamic voltage scaling (DVS), and MP operands planning to present optimum level of performance for varied operative conditions. varied techniques at the various levels of the planning method are enforced to cut back the time delay at the circuit, subject area and system level. The high performance is obtained by employing a new data structure, these adders area unit referred to as compressors. These compressors create the multipliers quicker as compared to the standard style. The additional amounts of element space and power needs area unit reduced owing to reconfigurable structures. during this paper we tend to style the number in 3 ways and compare their performance. victimization Model Sim half dozen.3f software package we are able to style the number structure and Xilinx synthesis Tool is employed for power and space analysis.