Forming voltage scaling of resistive switching memories

Metal oxide based resistive random-access-memory (RRAM) often requires a forming process before stable resistive switching can be achieved. Electrical forming usually involves voltages higher than normal switching conditions. It presents a design challenge because additional peripheral circuitry may be needed for this one-time process. RRAM is generally considered highly scalable owing to the filamentary conduction and switching mechanism; however, the forming properties have to be considered in a realistic assessment of RRAM scalability. Experiments have shown that RRAM forming voltage usually increases when device size scales down. This paper presents a simplified model to quantitatively analyze the area scaling of forming voltages. Statistical distribution of forming voltages can be simulated with a variable-resistor network model. Solutions to reduce the impact of forming process are needed for truly scalable RRAM technologies.