CCD Based New Domino Circuit Using Clamped bit line sense amplifier

In this paper, Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. The proposed circuit technique decreases the parasitic capacitance on the dynamic node, yielding a smaller keeper for wide fan-in gates to implement fast and robust circuits. Thus, the contention current and consequently power consumption and delay are reduced. The leakage current is also decreased by exploiting the footer transistor in diode configuration. In this new domino transistor using 4-bit OR Gate with 8 transistor are used. Simulation is done by using Tanner tool. Post-layout simulation results in a 0.18-μm CMOS technology confirm the analysis results. It is shown that in the proposed current comparison based domino reduces both the leakage current and delay time.