A 3 V 200 MHz PLL with a low-noise VCO based on a power-efficient low-ripple DC-DC converter

Author

Lee, Seung-Chul ; Lee, Joon-Seok ; Lee, Sung-Ho ; Lee, Seung-Hoon

Author_Institution

Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

346

Lastpage

348

Abstract

This paper describes a phase-locked loop (PLL) clock generator with low sensitivity to power supply noise. A voltage controlled oscillator employing a source follower reduces power supply noise sensitivity with the proposed power-efficient low-ripple DC-DC converter. Simulated clock jitter is less than ±20 ps, with a 200 mV peak-to-peak sinusoidal noise signal of 1 MHz to 400 MHz applied to a power supply. The proposed PLL simulated in a 0.65 μm double-poly double-metal CMOS process consumes 27 mW at 200 MHz from a 3 V supply. The prototype is under fabrication

Keywords

CMOS analogue integrated circuits; DC-DC power convertors; circuit simulation; clocks; integrated circuit noise; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; timing jitter; voltage-controlled oscillators; 0.65 mum; 200 MHz; 27 mW; 3 V; PLL clock generator; PLL simulation; clock jitter; double-poly double-metal CMOS process; low-noise VCO; mixed-signal ICs; peak-to-peak sinusoidal noise signal; phase-locked loop; power supply noise sensitivity; power-efficient low-ripple DC-DC converter; source follower; voltage controlled oscillator; Clocks; DC-DC power converters; Jitter; Noise generators; Noise reduction; Phase locked loops; Phase noise; Power generation; Power supplies; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820928

Filename

820928