Digital to analog converter for the analog front end of the WiMAX applications

In this paper, a one-dimensional linear gradient error compensation in current-steering is implemented in the digital-to-analog (DAC) arrays. A new approach of current cells optimal switching sequences that have a minimum variance of error is proposed. The proposed DAC adapts a 4-4-2 segmentation architecture to achieve high speed application. The simulation results show that the proposed design can achieve less than 0.065 LSB INL and 0.055 LSB DNL. The DAC is realized in a 1P6M 0.18-μm CMOS process. The power supply is 1.8V and the power consumption is less than 25 mW. At this low supply environment, the circuit can still achieve a 250Ms/s and a 10-bit resolution.