Static implementation of quasi-delay-insensitive Pre-Charge Half-Buffers

In the literature, quasi-delay-insensitive (QDI) asynchronous circuits utilizing Pre-Charge Half Buffers (PCHB) are based on either dynamic or semi-static implementations. In this paper, a static implementation of PCHB is presented, and compared to previous PCHB architectures and static NULL Convention Logic (NCL), using a full adder design. Transistor level simulation shows that the static PCHB architecture is faster, more energy-efficient, and can operate correctly at much lower supply voltage than its semi-static counterpart, although it requires more transistors. Compared to static NCL, static PCHB is faster and requires fewer transistors, but is less energy-efficient.