DocumentCode
1576799
Title
Retiming for high speed and low power design
Author
Kim, Hyun-Gyu ; Oh, Hyeong-Cheol
Author_Institution
Dept. of Electron. & Inf. Eng., Korea Univ., Seoul, South Korea
fYear
1999
fDate
6/21/1905 12:00:00 AM
Firstpage
395
Lastpage
398
Abstract
The positioning of flip-flops in a sequential circuit is related to the power dissipation as well as the clock period of the circuit. We show that genetic algorithms can be used to find efficiently the optimal positioning for the power performance of CMOS digital circuits without sacrificing the clock periods. As the result of evaluating our design method, we reduce dissipation of power about 9-10% with preserving optimal clock period
Keywords
CMOS logic circuits; circuit optimisation; flip-flops; genetic algorithms; high-speed integrated circuits; integrated circuit design; low-power electronics; sequential circuits; timing; CMOS digital circuit; clock period; flip-flop; genetic algorithm; high-speed low-power design; optimization; power dissipation; retiming; sequential circuit; CMOS digital integrated circuits; Capacitance; Clocks; Design engineering; Digital circuits; Equations; Flip-flops; Genetic algorithms; Power dissipation; Power engineering and energy;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-5727-2
Type
conf
DOI
10.1109/ICVC.1999.820942
Filename
820942
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