An enhanced architecture for high performance BIST TPG

This paper proposes a methodology to generate the multiple test patterns varying in single bit position for built-in-self-test (BIST). The traditional patterns which were generated using Linear feedback shift registers lack correlation between consecutive test vectors. So, in order to improve correlation between the subsequent test vectors, the patterns were produced using Gray counter and Decoder. The Area optimization is achieved by reducing the total number of gate count to implement the design. In order to optimize the power, the number of toggles between the subsequent test vectors is curtailed. The generated test patterns have an advantage of minimum transition sequence. Simulation results on multiplier circuit shows a reduction of 54% in area overhead and 12% in power overhead compared to pattern generation using Reconfigurable Johnson counter and LFSR. 100% fault coverage is achieved while generating patterns using gray counter, decoder and accumulator architecture. Time coverage is same as time required for generating patterns using existing methodology. The methodology for producing the test vectors for BIST is coded using VHDL and simulations were performed with ModelSim 10.0b. The Area utilization and the power report were obtained with the help of Xilinx ISE 9.1 software.