• DocumentCode
    1577189
  • Title

    Compression of partially specified test vectors in an ATE environment

  • Author

    Karimi, F. ; Kim, Y.B. ; Lombardi, F. ; Park, N.

  • Author_Institution
    LTX Corp., San Jose, CA, USA
  • Volume
    2
  • fYear
    2003
  • Firstpage
    999
  • Abstract
    The manufacturing test of today´s digital chips requires new design considerations for automatic test equipment (ATE). Compression has been used in ATE to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. This paper deals with compression of partially specified test sets, i.e. vectors with don´t care (unspecified, X) entries. A proper X assignment can be used to enhance the potential for compression by introducing similarities among vectors (correlation). This paper provides a comprehensive treatment of the X assignment for compression within fixed order and reordered test sets. For fixed order the X assignment is based on a novel technique referred to as bit-wise correlation. Using a matrix representation of the test set, X entries located in the same position in the vectors are analyzed and Boolean values assigned based on three criteria (column-wise bit-correlation). Once the fully specified test set is generated, an appropriate compression technique is used. If reordering is allowed, the process of X assignment is substantially different. Reordering is accomplished through a variation of column-wise bit-assignment, namely pair-wise bit-correlation. Pair-wise bit-correlation restricts the analysis to vector pairs as a heuristic condition for generating the new ordered test set. Simulation results are provided to support the viability of the proposed approach to compress test set with partially specified vectors.
  • Keywords
    automatic test equipment; compressive testing; correlators; ATE; automatic test equipment; bit-wise correlation; partially specified test vector; reordering; Costs; Decoding; Hardware; Integrated circuit testing; Linear feedback shift registers; Logic testing; Manufacturing; Performance evaluation; System testing; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Instrumentation and Measurement Technology Conference, 2003. IMTC '03. Proceedings of the 20th IEEE
  • ISSN
    1091-5281
  • Print_ISBN
    0-7803-7705-2
  • Type

    conf

  • DOI
    10.1109/IMTC.2003.1207902
  • Filename
    1207902