DocumentCode
1577421
Title
Modeling for synthesis in VHDL
Author
Moretti, Gabe S.
Author_Institution
Intergraph, Mountain View, CA, USA
fYear
1993
Firstpage
278
Lastpage
282
Abstract
VHDL is a rich modeling language supporting a vast range of abstractions. To efficiently use present day synthesis, the modeler must follow a style that differs considerably from the one required by logic simulators. In this tutorial, a guide to the efficient use of available synthesis tools is provided
Keywords
application specific integrated circuits; circuit layout CAD; hardware description languages; logic CAD; VHDL; logic synthesis; modeling language; multi-ASIC system; synthesis tools; tutorial; Algorithm design and analysis; Circuit synthesis; Costs; Documentation; Hardware design languages; Libraries; Logic design; Signal synthesis; Silicon; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-1375-5
Type
conf
DOI
10.1109/ASIC.1993.410722
Filename
410722
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