Title :
W CMP evaluation for 0.25 μm logic device
Author :
Lee, Jong-Hyup ; Kwon, Byoung-Ho ; Lee, Se-Young ; Kim, Hee-Jeen ; Ryu, Young-Gyoon ; Kweon, SeongSoo ; Lee, Jeong-Gun
Author_Institution :
Syst. IC R&D Center, Hyundai Electron. Ind. Co. Ltd., Kyoungki, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
The purpose of this study is to report polishing characteristics of W CMP with combination sets of slurry and pad in 0.25 um logic technology. W etch back process is compared with W CMP process in view of electrical performance in the 0.25 μm logic device. The proper selection of consumables is important to the successful application of W CMP. The W CMP process should be carefully controlled to be implemented in the back-end process of sub-quarter micron logic device
Keywords :
VLSI; chemical mechanical polishing; integrated circuit metallisation; integrated logic circuits; tungsten; 0.25 micron; W; W CMP evaluation; W etch back process; back-end process; electrical performance; polishing characteristics; sub-quarter micron logic device; Electric variables measurement; Electrical resistance measurement; Electronics industry; Etching; Inspection; Logic devices; Logic testing; Performance evaluation; Research and development; Slurries;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.820969
