Power implications of additions in floating point DSP-an architectural perspective

This work targets experimental characterization of the architectural power implications of floating point adders that form part of DSP cores. High level models that characterize the power behavior of floating point adders are developed. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. The experiments substantiate the validity of our transition activity scaling based approach for the design of low power floating point adders. The worst case power reduction offered by the proposed transition activity scaled triple data path floating point adder (TDPFADD) is consistently above 50%. The corresponding reduction in power delay product is better than 70%