Title :
System level verification of ASIC chip-sets
Author :
Tayal, Sanjaya ; Moezzi, Ali ; Magnusson, Eric
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
A methodology for providing pre-silicon system validation of ASIC chip-sets in a universal, VHDL system model is presented. System level simulation is an invaluable technique to reduce bugs in chip design. Tests written for the system exercise a chip in a system environment, which is difficult to reproduce at full chip testing. The techniques outlined were used on Intel´s 82429/82430 PCIset. Some critical bugs were identified at the pre-silicon stage. The PCIset booted essential PC software at the first turn of silicon
Keywords :
application specific integrated circuits; automatic test software; circuit analysis computing; formal verification; hardware description languages; integrated circuit design; logic CAD; logic testing; system buses; ASIC chip-sets; Intel´s 82429/82430 PCIset; VHDL system model; automated test generation; critical bugs; peripheral component interconnect; pre-silicon system validation; regression testing; standard local bus; system level simulation; system level verification; Application specific integrated circuits; Bridges; Cities and towns; Instruction sets; Laser sintering; Logic functions; Logic testing; Microcomputers; Software testing; Writing;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410723
