VLSI implementation of an efficient Fused Add-Multiply unit using Constant-time addition

Digital Signal Processing (DSP) applications widely use complex arithmetic operations. This paper introduces an implementation of one of the complex arithmetic operations, the Fused Add-Multiply (FAM) operation. In general, a separate adder and a multiplier are used to perform Add-Multiply operation. The use of separate adder and multiplier adds significant area and delay. So, an efficient Fused Add-Multiply Unit is implemented using the Radix-8 Modified Booth Recoder. The Modified Booth Recoder design is based on the redundant logic and Constant-time addition. Instead of deriving the adder output as in conventional methods, the recoder recodes the adder input directly to MB form thus decreasing delay. The multiplier unit uses the Radix-8 Modified Booth algorithm. The delay and the area of the redundant adder/recoder have been reduced by 2% and 57% respectively. In comparison with the conventional design, the overall delay of the FAM has been reduced by 15%. On analyzing the Radix-8 FAM unit, it has been observed that the newly modified design yields better performance in terms of area and delay.