High speed, energy efficient master-slave flip-flops

In modern VLSI circuits, a clock system consumes 20-45% of the total chip power. In the clock system power, about 90% is consumed by the flip-flops themselves. In addition, to get higher clock frequency, leading microprocessors use deep pipelining which need more DFFs. Meanwhile, low energy circuit techniques are required for portable systems such as notebook PC or palmtop, etc. Therefore, enhancing DFF´s speed and reducing its power consumption are becoming important. In this paper, we propose a modified push-pull isolation register and a modified split-slave dual-path register to enhance speed and reduce energy consumption. The two proposed flip-flops improve the energy efficiency of the prior type by 7.3% and 14.7% respectively, due to mainly speed improvement and slight power saving. The above results are verified with 3.3 V 0.6 μm, 1 poly 3 metal, CMOS technology