DocumentCode :
1578156
Title :
Hardware Reuse in Modern Application-Specific Processors and Accelerators
Author :
Nery, Alexandre S. ; Jozwiak, Lech ; Lindwer, Menno ; Cocco, Mauro ; Nedjah, Nadia ; França, Felipe M G
Author_Institution :
LAM-Comput. Archit. & Microelectron. Lab., Univ. Fed. do Rio de Janeiro, Rio de Janeiro, Brazil
fYear :
2011
Firstpage :
140
Lastpage :
147
Abstract :
Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.
Keywords :
application specific integrated circuits; instruction sets; logic design; microprocessor chips; reconfigurable architectures; ASIP; academic collaborative research; accelerator synthesis; application-specific accelerators; application-specific parallel patterns; application-specific processors; application-specific reconfigurable application specific instruction set processors; circuit parameter; computation operations; hardware accelerators; hardware reuse; hardware sharing; high-quality application-specific reconfigurable application specific instruction set processors; multiobjective optimization; state-of-the-art synthesis tools; system parameter; tradeoff exploitation; Adders; Computer architecture; Delay; Hardware; Optimization; Program processors; Resource management; Application-Specific Processors; Area Reduction; Hardware Accelerator; Power Reduction; Resource Sharing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
Type :
conf
DOI :
10.1109/DSD.2011.22
Filename :
6037403
Link To Document :
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