A folded bit-line architecture for high speed CMOS SRAM

Author

Kim, Sejun ; Chang, Ilkwon ; Seo, Seungyoung ; Kwack, Kaedal

Author_Institution

Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

553

Lastpage

556

Abstract

This paper describes a new architecture and schemes for a high speed SRAM. It is summarized as follows:1) a Folded Bit-Line Architecture (FBLA) to reduce the delay time of bit-line by decreasing the parastic capacitance, to reduce the area. 2) a Double Word-Line Activation (DWLA) technique to increase the data-rate twice and minimize row path delay, and 3) a high speed sensing scheme to decrease the delay time of the sense amplifier. To verify the above, a 8 kb SRAM was designed using 0.6 μm CMOS technology. It realized a 600 Mbyte/s(300 M×8×2) data-rate and the die size is 2.8 mm×0.85 mm

Keywords

CMOS memory circuits; SRAM chips; capacitance; high-speed integrated circuits; memory architecture; 0.6 micron; 1.41 ns; 300 MHz; 600 Mbyte/s; 8 kbit; bit-line delay time reduction; double word-line activation technique; folded bit-line architecture; high speed CMOS SRAM; high speed sensing scheme; parastic capacitance reduction; row path delay minimisation; Capacitance; Circuits; Clocks; Decoding; Delay effects; Electronic mail; Logic gates; Microprocessors; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820998

Filename

820998