Title :
A fast lock-on time mixed mode DLL with 10 ps jitter
Author :
Han, Seon-Ho ; Lee, Joo-Ho ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
We propose a mixed mode Delay Locked Loop (DLL) for low jitter clock recovery and fast lock-on time. A digital FDL (Fixed Delay Line) compensates initial large phase error and an analog VCDL (Voltage Controlled Delay Line) compensates small static phase error to obtain low jitter. The lock-on time of the mixed mode DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz
Keywords :
CMOS integrated circuits; delay lock loops; error compensation; high-speed integrated circuits; mixed analogue-digital integrated circuits; synchronisation; timing jitter; 10 ps; 200 MHz; analog voltage controlled delay line; digital fixed delay line; fast lock-on time DLL; low jitter clock recovery; mixed mode DLL; phase error; Circuit simulation; Clocks; Delay effects; Delay lines; Frequency synchronization; Jitter; Laser mode locking; Phase frequency detector; Phase locked loops; Voltage control;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.821001
