ASIC system design considerations

Author

Shastry, Nanjunda

Author_Institution

Toshiba American Electronic, Components, Inc., Sunnyvale, CA, USA

fYear

1993

Firstpage

294

Lastpage

296

Abstract

This tutorial focuses on reducing interchip delays using performance controlled circuitry (PCC). Variations in CMOS ASIC temperature, voltage, and IC manufacturing process all cause variations in performance, especially I/O switching performance. Variations in I/O switching performance are no longer tolerable in today´s high-performance system designs where interchip timing and communications is critical. PCC and PCC I/Os increase I/O switching performance while minimizing noise. The PCC compensates the PCC I/Os in real time and increases the entire system´s performance

Keywords

CMOS logic circuits; application specific integrated circuits; buffer circuits; compensation; impedance matching; integrated circuit noise; logic design; timing; ASIC system design; CMOS ASIC; I/O switching; IC manufacturing process; clock skew; high performance buffer; high-speed systems; impedance matching; interchip communications; interchip delays; interchip timing; noise minimization; performance controlled circuitry; real time compensation; temperature; tutorial; variations in performance; voltage; Application specific integrated circuits; CMOS integrated circuits; CMOS process; Communication switching; Communication system control; Delay; Manufacturing processes; Temperature; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410725

Filename

410725