A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive

Author

Kim, Jin-Cheon ; Lee, Sang-Hoon ; Park, Hong-June

Author_Institution

Dept. of Electr. Eng., POSTECH, Pohang, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

574

Lastpage

577

Abstract

A half-swing clocking scheme with a complementary gate and source drive was proposed for CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time to be the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of flip-flop using this scheme is less than half that using the previous half-swing clocking scheme

Keywords

CMOS logic circuits; clocks; flip-flops; high-speed integrated circuits; low-power electronics; CMOS flip-flop; complementary gate and source drive; delay time; high-speed low-power half-swing clocking scheme; power consumption; Capacitance; Clocks; Delay effects; Driver circuits; Energy consumption; Flip-flops; Latches; Strontium; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.821004

Filename

821004

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1578376