DocumentCode
157840
Title
MemZip: Exploring unconventional benefits from memory compression
Author
Shafiee, Ali ; Taassori, Meysam ; Balasubramonian, R. ; Davis, A.K.
Author_Institution
Univ. of Utah, Salt Lake City, UT, USA
fYear
2014
fDate
15-19 Feb. 2014
Firstpage
638
Lastpage
649
Abstract
Memory compression has been proposed and deployed in the past to grow the capacity of a memory system and reduce page fault rates. Compression also has secondary benefits: it can reduce energy and bandwidth demands. However, most prior mechanisms have been designed to focus on the capacity metric and few prior works have attempted to explicitly reduce energy or bandwidth. Further, mechanisms that focus on the capacity metric also require complex logic to locate the requested data in memory. In this paper, we design a highly simple compressed memory architecture that does not target the capacity metric. Instead, it focuses on complexity, energy, bandwidth, and reliability. It relies on rank subsetting and a careful placement of compressed data and metadata to achieve these benefits. Further, the space made available via compression is used to boost other metrics - the space can be used to implement stronger error correction codes or energy-efficient data encodings. The best performing MemZip configuration yields a 45% performance improvement and 57% memory energy reduction, compared to an uncompressed non-sub-ranked baseline. Another energy-optimized configuration yields a 29.8% performance improvement and a 79% memory energy reduction, relative to the same baseline.
Keywords
data compression; error correction codes; memory architecture; meta data; MemZip configuration; bandwidth demands; capacity metric; complex logic; compressed data; compressed memory architecture; energy reduction; energy-efficient data encodings; energy-optimized configuration; error correction codes; memory compression; memory system; metadata; page fault rate reduction; rank subsetting; uncompressed nonsubranked baseline; unconventional benefits; Bandwidth; DRAM chips; Delays; Encoding; Memory management; Reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/HPCA.2014.6835972
Filename
6835972
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