Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance

In this paper, we investigate the mechanism of soft error generation, propagation in asynchronous circuits which are implemented on FPGA. We also proposed the circuit to detect the soft errors which propagate in asynchronous Pipelines. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed and detected. The simulation results show that the proposed detect circuit can detect the soft error in asynchronous circuits implemented on FPGAs easily so that FPGAs can be reprogrammed, compared with traditional synchronous circuits.