An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion

Overlapped Block Motion Compensation (OBMC) technique is used to avoid blocking artifacts occurring because of block based processing in video enhancement and compression applications. In this paper, we propose Weighted Coefficient OBMC (WC-OBMC) algorithm and an efficient hardware architecture for its implementation. WC-OBMC produces high quality results with low computational complexity for frame rate up conversion of High Definition (HD) video. The proposed hardware implementation of WC-OBMC algorithm consumes 20% of the slices in a Xilinx XC6SLX9-2 FPGA. It can work at 65 MHz in the same FPGA, and it is capable of processing 31 1280x720 HD frames per second.