Title :
FPGA implementation of efficient AES encryption
Author :
Priya, S. Sridevi Sathya ; Karthigai Kumar, P. ; SivaMangai, N.M. ; Rejula, V.
Author_Institution :
Dept. of Electron. & Commun. Eng., Karunya Univ., Coimbatore, India
Abstract :
In this paper, a high throughput modified Advanced Encryption Standard (AES)-128 bit algorithm is implemented. A new increased parallelism technique is introduced in modified AES architecture in Mix Column round which increases the overall throughput of AES algorithm. This technique is implemented in XC5VLX50T FPGA device Virtex-5. Using this technique throughput is increased 5 % and area is decreased by 30 % when compared to parallel mixcolumn.
Keywords :
cryptography; field programmable gate arrays; AES encryption; XC5VLX50T FPGA device Virtex-5; advanced encryption standard; mix column round; Ciphers; Encryption; Field programmable gate arrays; Parallel processing; Standards; Throughput; AES; high throughput; increased Parallelism; latency; throughput;
Conference_Titel :
Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-6817-6
DOI :
10.1109/ICIIECS.2015.7193081
