• DocumentCode
    1578792
  • Title

    An FPGA-Based Implementation of Spatio-Temporal Object Segmentation

  • Author

    Ratnayake, K. ; Amer, Aishy

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
  • fYear
    2006
  • Firstpage
    3265
  • Lastpage
    3268
  • Abstract
    This paper proposes a robust real-time, scalable and modular field programmable gate array (FPGA) based implementation of a spatio-temporal segmentation of video objects. The goal of this work is to translate an existing object segmentation algorithm into hardware to achieve real-time performance. The proposed implementation achieved an optimum processing speed of 133 MPixels/s while utilizing minimal hardware resources. The design was successfully simulated, synthesized and tested for real-time performance on an actual hardware platform which consists of a frame grabber with a user programmable FPGA - Xilinx Virtex-II Pro.
  • Keywords
    field programmable gate arrays; hardware description languages; image segmentation; spatiotemporal phenomena; video signal processing; VHDL; Xilinx Virtex-II Pro; frame grabber; modular field programmable gate array; real-time scalable FPGA-based implementation; spatio-temporal object segmentation algorithm; video object; Digital signal processing; Field programmable gate arrays; Hardware; Image segmentation; Motion detection; Object segmentation; Signal processing algorithms; Signal synthesis; Stability; Testing; Field programmable gate arrays; Image segmentation; Video signal processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Image Processing, 2006 IEEE International Conference on
  • Conference_Location
    Atlanta, GA
  • ISSN
    1522-4880
  • Print_ISBN
    1-4244-0480-0
  • Type

    conf

  • DOI
    10.1109/ICIP.2006.312920
  • Filename
    4107267